Recent growth in portable, battery-operated devices has fueled the growth of the low dropout (LDO) voltage regulator market. The LDO regulator is characterized by its low dropout voltage. Dropout voltage is the difference between the LDO regulator's input voltage (an unregulated voltage received from an unregulated source, such as a battery or a transformer) and the LDO regulator's output voltage (regulated voltage). LDO regulators are particularly useful in portable devices such as portable telephones, pagers, personal digital assistants (PDA), portable personal computers, camcorders, digital cameras, etc.
FIG. 1 diagrammatically illustrates an LDO regulator circuit according to the prior art. The LDO regulator of FIG. 1 includes an amplifier stage A having a non-inverting input 11 and an inverting input 12, and having an output 13. In the example of FIG. 1, an input terminal 16 is coupled to the non-inverting input 11 by a resistor R3. The output 13 of the amplifier A is coupled to the gate of a P-channel transistor P which forms an output stage of the LDO regulator. The source terminal 14 of transistor P is coupled to the positive power supply rail 17, and the drain terminal 15 of transistor P is coupled to a load L. Resistor R1 is coupled between the drain 15 of transistor P and the inverting input 12 of amplifier stage A. Resistor R1 and a further resistor R2 form a feedback control loop circuit 19 that sets the gain of the LDO regulator.
In some applications, for example GSM cellular telephones, the load L of FIG. 1 is an RF amplifier for amplifying RF communication signals and transmitting the amplified signals 47 on an RF communication channel according to a TDMA (time division multiple access) scheme. The LDO regulator output at 15 controls TDMA operation of the RF amplifier in response to the LDO input at 16. The input terminal 16 can be driven by a precision ramp signal provided by a high performance digital-to-analog converter (DAC) in a baseband IC of the cellular telephone. In such applications, adjacent channel interference and sideband noise are to be avoided, so noise and linearity are a major concern. Moreover, it is well known that the sideband noise typically gets worse when the LDO is near saturation. The dynamic range is effectively reduced, and the noise floor increases.
When the amplifier stage A enters the saturation mode, power supply rejection reduces to near zero. This is because the amplifier A turns on the transistor P as hard as possible, so P no longer acts as a current source, but rather becomes a resistor which has no power supply rejection. When the amplifier A enters the saturation mode and the transistor P is turned on as hard as possible, this is a condition from which recovery can be difficult.
FIG. 2 illustrates an example of a saturation phenomenon observed in conventional LDO regulators. The input ramp signal at 16 causes the amplifier A to ramp up into the saturation region, turning on the transistor P as hard as possible, so the drain voltage 15 reaches the supply rail voltage of 3.5 volts. When the input signal 16 ramps back down, the LDO cannot easily recover from the saturation condition, so the falling edge of the voltage signal at drain 15 initially exhibits a near vertical step-down response followed by significant noise ringing, both of which are undesirable in RF communications. Moreover, the problem is typically exaggerated by the inductance associated with product packaging.
FIG. 3 also illustrates the response of the drain 15 to the input signal 16 of FIG. 1, together with the response of an internal node 31 within the amplifier A. As shown in FIG. 3, the internal node 31 experiences undesirable noise ringing associated with the falling edge ringing on drain 15.
It is desirable in view of the foregoing to provide an LDO regulator which can avoid the difficulties presently associated with recovering from operation in the hard saturation mode.